1. Field of Invention
The presented application relates to a capacitor structure and a method for manufacturing the same, in particular, to an integrated capacitor structure using in an embedded memory device and a method of manufacture.
2. Description of Prior Art
There is a great demand for an integrated capacitor formed on a substrate in the field such as cellular phones. The integrated capacitor can be used in an analogous circuit and an RF circuit where a capacitance value of above pF is typically required. However, the maximum value of planar capacitance density, which can be achieved in the current integrated circuit process, is about tens of fF/μm2. In order to achieve the capacitance value of above pF, the resultant capacitor must have a relatively large footprint on the chip. This decreases an integration level, and causes an undesired parasitic effect due to those wirings having an increased length. Moreover, when used in an embedded memory (such as eDRAM) in a digital circuit, the capacitance value of a memory cell is of critical importance to a retention time of the device. In order to achieve a retention time as long as possible for each memory cell, an integrated capacitor should have a capacitance density as large as possible.
Wang Geng et al. proposed an eDRAM cell having a deep trench capacitor formed in a substrate in U.S. patent application US20090174031A1. Sidewalls of the trench provide most area of a capacitor plate, which reduces a footprint of the eDRAM cell on the surface of the chip, while providing a large capacitance value.
However, the eDRAM cell comprising a deep trench capacitor still has many difficulties in manufacturing process. For example, since a deep trench has a high aspect ratio, a reactive ion etching (RIE) process will take a long time for forming the deep trench, and voids possibly exist in the following metal filling process.
Consequently, the deep trench capacitor has a high manufacturing cost and a poor reliability.
On the other hand, the above difficulties in the manufacturing processes limit the depth of the trench to be formed. The resultant capacitance value is too small to provide a desired retention time of the eDRAM cell.
Yasuo Watanabe et al. proposed a multi-layer ceramic capacitor in U.S. patent application US20050095851A1 which comprises a stack of a dielectric layer paste and an internal electrode paste and includes a sintering step. Although the multi-layer ceramic capacitor structure has a reduced surface area, it is not compatible with a conventional integrated circuit process.